The present invention relates to an electrode structure including a silicon-containing film containing silicon as a principal constituent, a barrier metal layer formed on the silicon-containing film and a metal film with a high melting point formed on the barrier metal layer, and a method for fabricating the electrode structure.
In a conventional MOS transistor, the gate electrode is formed from a polysilicon film. In accordance with increased refinement and operation speed of LSIs, there are increasing demands for lowering the resistance of a gate electrode of a MOS transistor.
For the purpose of lowering the resistance of a gate electrode, technique to use, as a gate electrode, a polymetal gate electrode of a multi-layer film including a lower polysilicon film and an upper metal film with a high melting point is proposed, and a tungsten film is proposed for use as the upper metal film with a high melting point. When a tungsten film is used as the upper metal film with a high melting point, the resistance of the gate electrode can be lowered.
It is necessary to form, between the polysilicon film and the tungsten film, a barrier metal layer of, for example, titanium nitride (TiN) for preventing a dopant (such as B, P and As) introduced into the polysilicon film from diffusing into the tungsten film (as described in, for example, Japanese Laid-Open Patent Publication No. 11-261059).
FIG. 8 shows the cross-sectional structure of a multi-layer film obtained before forming a polymetal gate electrode by patterning. As shown in FIG. 8, a polysilicon film 3, a barrier metal layer 4 of a titanium nitride film and a tungsten film 5 are successively formed on a semiconductor substrate 1 with a gate insulating film 2 sandwiched therebetween. The polymetal gate electrode is formed by patterning the multi-layer film.
In the conventional polymetal gate electrode, the interface resistance between the polysilicon film 3 and the barrier metal layer 4 is disadvantageously high. Also, when the polymetal gate electrode is subjected to high temperature annealing, such as annealing for activating dopant layers serving as the source and the drain, the interface resistance becomes higher.
The present inventors have variously studied the cause of the high interface resistance between the polysilicon film 3 and the barrier metal layer 4, resulting in finding the following. Now, the reasons why the interface resistance between the polysilicon film 3 and the barrier metal layer 4 is high and why the interface resistance becomes higher through high temperature annealing will be described with reference to FIGS. 9A and 9B.
FIG. 9A shows the cross-sectional structure, observed with a TEM (transmission type electron microscope), of a multi-layer film, which is to be patterned into a polymetal gate electrode, formed by successively depositing a barrier metal layer 4 of titanium nitride and a tungsten film 5 on a polysilicon film 3. On the interface between the polysilicon film 3 and the barrier metal layer 4, a reaction layer 6 of a compound (SiN) principally including silicon (Si) and nitrogen (N) having a very high resistance value is formed. Owing to the reaction layer 6, the interface resistance between the polysilicon film 3 and the barrier metal layer 4 is high.
FIG. 9B shows the cross-sectional structure, observed with a TEM, of the multi-layer film to be patterned into a polymetal gate electrode obtained after subjecting it to high temperature annealing. As is understood from comparison between FIGS. 9A and 9B, the reaction layer 6 is increased in its thickness because the reaction between silicon and nitrogen is proceeded through the high temperature annealing. Accordingly, the interface resistance between the polysilicon film 3 and the barrier metal layer 4 becomes higher.
Now, the procedures for successively depositing a barrier metal layer 4 of titanium nitride and a tungsten film 5 on a polysilicon film 3 will be described with reference to FIGS. 10A through 10C.
First, as shown in FIG. 10A, a polysilicon film 3 is deposited on a semiconductor substrate 1 with a gate insulating film 2 sandwiched therebetween, and the resultant semiconductor substrate 1 is placed in a first chamber A in which a titanium target 7 including titanium as a principal constituent is disposed. Thereafter, a mixed gas of an argon gas and a nitrogen gas (in which the partial pressure ratio (volume flow ratio) of the nitrogen gas is approximately 60%) is introduced into the first chamber A, and discharge is caused in the first chamber A. Thus, plasma of the argon gas and the nitrogen gas is generated, so that a reaction layer 6 of a compound including silicon and nitrogen as principal constituents can be formed on the polysilicon film 3 through a reaction between nitrogen ions included in the plasma and silicon included in the polysilicon film 3.
When the discharge is continuously caused in the first chamber A, a titanium nitride film 8 is formed on the titanium target 7 and the titanium nitride film 8 is sputtered so as to form a barrier metal layer 4 of titanium nitride on the reaction layer 6 as shown in FIG. 10B.
Next, after the resultant semiconductor substrate 1 is placed in a second chamber B in which a tungsten target 9 including tungsten as a principal constituent is disposed, an argon gas is introduced into the second chamber B and discharge is caused in the second chamber B. Thus, the tungsten target 9 is sputtered so as to deposit a tungsten film 5 on the barrier metal layer 4.
Subsequently, dopant layers serving as the source and the drain of the MOS transistor are formed in the semiconductor substrate 1, and annealing is carried out at a temperature of 750 or more for activating the dopant layers. Thus, excessive nitrogen included in the barrier metal layer 4 of titanium nitride and silicon included in the polysilicon film 3 are reacted with each other, resulting in increasing the thickness of the reaction layer 6 as shown in FIG. 9B.
When the interface resistance between the polysilicon film 3 and the barrier metal layer 4 is high and therefore the interface resistance between the polysilicon film 3 and the tungsten film 5 is high, the operation speed of the MOS transistor is lowered. Specifically, when the gate electrode is operated with AC (alternating current), distributed capacitance generated in the gate insulating film is repeatedly charged and discharged. Therefore, a current flows through the distributed interface resistance, and hence, the distributed interface resistance affects to lower the operation speed of the MOS transistor. When the operation speed of the MOS transistor is lowered, the operation speed of the entire LSI is lowered, so as to disadvantageously increase signal delay time. Since the operation speed of an LSI is regarded to be the most significant today, the lowering of the operation speed of the MOS transistor by merely several % becomes a serious problem.
In order to prevent the delay time of the MOS transistor from lowering, the interface resistance between the polysilicon film and the metal film with a high melting point should be 200 Ùm2 or less.